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# Cross Conduction in Modern Power MOSFETs

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Alan Elbanhawy

Power industry consultant, email: aelbanhawy@igcorporation.com

Introduction

The synchronous buck converter is the DC-DC converter of choice in PC and notebook computers and has been so for many years. This topology provides ease of control and high power conversion efficiencies at a relatively low cost and within a small footprint. One of the keys to success in designing a synchronous buck converter is limiting the shoot-through or cross-conduction current. This phenomenon can cause excessive losses which leads to poor performance and results in low power conversion efficiency. Mathematical formulae will be derived that allow MOSFET and power supply designers to test the suitability of a specific device for its use as a synchronous rectifier in this converter.

Choosing the Right MOSFETShoot-through may be explored by examining the factors that control the induced gate-source voltage when the drain voltage is switched between near ground and input voltage, Vcc,  levels. This situation is encountered in the Synchronous Buck topology (Figure 1) during the time interval when the top or control MOSFET, MHS, is switched ON while the PWM controller holds OFF the lower MOSFET or synchronous rectifier MLS. If the induced voltage is larger than the Gate Threshold Voltage of the MOSFET, MLS could be turned ON while the top MOSFET is ON. Since an ON MOSFET has a very low on-resistance in the order of few milliohms to a few tens of milliohms, this condition will result in fairly excessive currents flowing through both devices, leading to excessive power dissipation in both MOSFETs and ultimately to failure in either one or both devices. By examining the mechanism causing this phenomenon, proper MOSFET selection can be made and cross conduction can be eliminated or reduced to negligible levels.

Shoot-Through in the Synchronous Buck Converter A common synchronous buck converter is shown in Figure 1: Figure 1. A common synchronous buck converter using two N-channel MOSFETs.
The synchronous rectifier, M
LS, is shown with internal lumped parameters.

Assume the lower MOSFET, MLS, is initially turned OFF and the top MOSFET, MHS, turned ON. This applies the input voltage on one end of the inductor, causing the inductor current to ramp up. When MHS is turned OFF, the current will continue flowing through the inductor but now it flows through the body diode D1 of MLS. After a dead time on the order of a few tens of nanoseconds?dictated by the PWM controller?the MOSFET MLS turns ON. This allows all the inductor current now to flow through MLS rather than D1, since the voltage drop across its RDSON is much lower than the diode voltage drop. Assuming that the current through the inductor does not reach zero (the Continuous Conduction Mode), the voltage across the lower MOSFET will simply be = RDSON . ILOAD during the full on period of the MLS where RDSON  is the on-resistance and ILOAD is the inductor current ≈ the load current.

Assumptions

In the following analysis we will assume, for simplicity, that all the electrodes parasitic inductances are negligible. This will allow us to derive simple equations with reasonable accuracies.

Analysis

Figure 2 shows the lower MOSFET in the OFF state and its equivalent circuit for this analysis. Figure 2. Resistances, capacitances and voltages associated with the lower MOSFET in the
synchronous buck converter, equivalent circuit and V
in waveform.

The analysis begins by writing Kirchoff's equations for the equivalent circuit of MLS. Vin is a voltage source representing the effect of the external circuit as the top MOSFET , MHS, turns ON. The Drain Voltage , where a is the rate of change of the drain voltage and t is time. Kirchoff?s loop equation for this circuit yields:   =   Where and is the internal effective gate resistance and is the gate driver integrated circuit sink resistance. = Solving equations e11, e2 and e33 provides the value of current through the gate resistor:  = where i1t is the current flowing in the gate resistor Rg.

Now we can calculate the gate voltage: = The condition for no shoot-through in a given MOSFET under a given rate of change of the Drain Voltage a can be calculated using the Vg equation. At the end of the rise time, t=tr and Vin=Vcc (usually is 5V or 12V). At this instance, if Vg>Vgth (the MOSFET gate threshold voltage) cross conduction occurs. To find the value that will cause cross conduction, the equation of Vg can be derived by substituting :  (1)

For a very fast rise time we can take the limit of equation (1) to get the gate voltage Vglimit at a point where the rise time=0  i.e. .  (2)

Equation (2)  is a very important one since it indicates that if there will be no shoot-through for any value of a. This can be achieved in so many ways like reducing the value of Cgd or increasing Vgth or Cgs. Increasing Cgs is not a good idea since it will adversely affect the dynamic losses. Also, notice that the equation is independent of Rg, which is to be expected. As a gets larger, the reactance of Cgs becomes much smaller than Rg and it becomes the only determining factor, since both components are connected in parallel. Alternatively, if , then cross conduction can be expected at some level of a.Even if a MOSFET meets the condition in equation (2), it still may be suitable for the application as a synchronous rectifier as long as it satisfies equation (1) for an actual circuit rise time.    The above graph depicts both Vgl and the Vglimit. Clearly the gate voltage almost reaches the asymptotic value of Vglimit at .

In order to examine the range at which shoot-through occurs, we plot the gate voltage as a function of Cgd and a.   The above graph shows the Vgth plane at 1.2V and the induced gate voltage Vgl as a function of Cgd and a. All points above the Vgth plane should be expecting shoot-through at varying degrees proportional to the value of .

Worst Case Analysis

One last task we can do is to examine the suitability of a specific MOSFET for a 12 V application by evaluating the worst case MOSFET parameters conditions.

From the MLS datasheet, the MOSFET parameters are:

Cgs=3185pf..5915 pF        Cgd=441pf..819 pF      Rg=1..1.6 Ω       Vgth=1.35..2.4 Ω

We can use equation (1) to do the evaluation using a 3D graph as seen below. The use of 3D graphing is particularly useful to get a more complete view of the gate voltage over the full tolerance of  Cgd , Cgs and Vgth and effectively pinpointing the full range of the problem.     Vgl for and and gate threshold planes

at minimum and maximum gate thresholds of 1.4 and 2.4 V.

Identification of different curves.

As can be seen in the 3-D graph above, MLS with Vgth at the upper limit of tolerance of 2.4V have no shoot-through problems over the entire tolerance range of both Cgd  and Cgs. However for Vgth close to the lower limit of tolerance of 1.4V, designers should expect some significant shoot-through. The graph above right is there only to identify the different curves in relation to each other for reference.

Full Cycle Examination

Now that we have derived equations (1) and (2) that enable us to examine the propensity of a specific MOSFET for shoot-through,

let us have a look at the MOSFET's response to one full wave. Using the Heaviside function, the input voltage for a full cycle may be represented as follows:    Now we can solve the same set of Kirchhoff equations using the s domain familiar to all electrical engineers. This is done to examine voltages and currents at the beginning and end of a single pulse.        Of particular importance is the ilta because this current must flow in the gate driver of MLS without forcing it out of saturation and further aggravating the situation.    By plotting the current at two different risetimes, , we can clearly observe that the current is significantly higher in the case of as compared to that at . For the time being we need not concern ourselves with rise times faster than 1 ns since almost all converters operate at a lower value.

Now we can examine the effect of gate-drain capacitance, Cgd, on the value of the gate voltage Vga by plotting Vga as a function of both time and Cgd and keeping the remaining variables at a constant value.   One can observe that an MLS MOSFET with a higher Cgd value is more prone to shoot-through when compared to a lower value one.

Looking at one last plot of as a function of and time with the rest of the variables held constant, we can see the full range of currents that may be observed for different risetimes. This graph is very useful when designing synchronous buck converters because the current i1ta is also sinked by the output stage of the gate driver of MLS.

Most commercially available gate drivers can sink and source a maximum of about 2 A. This means that if i1ta is larger than the maximum gate driver current, the output stage will get out of saturation resulting in the gate voltage climbing even higher, resulting in a more serious shoot-through condition.  Conclusion:1. Equation (1) should be used to evaluate a given MOSFET's susceptibility to shoot-through for almost all applications today.
2. Equation (2) should be used for the projected applications of the next few years where the rise and fall times are in the sub-nanosecond range.
3. We ignored the effect of MOSFET electrode inductances to derive simple and reasonably accurate equations. The use of parasitic inductances makes the problem so complicated that a simple equation is not attainable.
4. Shoot-through rarely results in a catastrophic failure of the MOSFETs. In general, it results in modest to serious degradation of the converter efficiency, resulting in higher operation temperatures.

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