Conduction Loss
Alan Elbanhawy
Power industry consultant, email: aelbanhawy@igcorporation.com
Foreword
Modern scientific papers published all over the world play a major role in disseminating new ideas, concepts and innovations that have propelled the state of the art in technology to amazing heights in the last few decades. These papers, in my opinion, were missing one thing which is being interactive. That is, the ability of the reader to examine the raw data, the mathematical derivations of the formulae used in the paper and the ability to take a individualized look at the intermediate and final results. The Maple^{TM} document format provides all these features by allowing a single document to contain text, graphics, embedded objects and the best symbolic and numerical engine in the industry.
This paper/worksheet is an attempt to take advantage of all these features and uniquely allow the reader to explore a fresh view of the subject of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) conduction losses while giving him/her the opportunity to take a different look at the results obtained by the author while reading the detailed text of the paper. Feel free to generate different graphs or examine different packages or silicon by entering your own parameter set.
Abstract
As the PC makers push for DCDC converters delivering >150 A at output voltages ≤1V within the next few years, the semiconductor manufacturers are pushing to optimize their MOSFET by improving both the silicon and the packages to provide switching devices suitable for these challenges. In this paper we will address the parasitic resistance attributed to the package alone and in isolation from the silicon onresistance. We will show that in most of the traditional packages this resistance has a very strong frequency dependent component.
This means that at a switching frequency of about a few megahertz, this parasitic resistance will constitute a large percentage of the total device onresistance and hence influences the losses greatly. Based on this observation, we will concentrate on the topology of choice, the synchronous buck converter, and we will derive conduction loss equations that are frequency dependent and calculate actual losses and examine several effects that follow.
IntroductionIt is estimated that personal computers (PCs), notebook computers and servers annually use in excess of 500 million synchronous buck DCDC converters each year. This number alone justifies an indepth analysis of this very popular topology to enable engineers to refine their design process and save energy and help the environment at the same time. There are several loss mechanisms in this topology but, in this paper, we will concentrate on the conduction loss alone.
Traditionally, the conduction loss, , in power MOSFETs has been calculated from the formula where is the inductor current, is the MOSFET's onresistance plus the package parasitic resistance and is the duty cycle. In this formula, the assumption is that the package parasitic resistance is a constant and is independent of frequency. However, a closer look at the package (see Figure 2) reveals that the bonding wires are thin enough with a diameters of few thousands of an inch that points towards possible skin effect influence on the parasitic resistance.In this paper we explore the influence of skin effect on power MOSFET's parasitic resistance. Formulae will be derived to express the package parasitic resistance as a function of frequency and power loss will be calculated to demonstrate the percentage error that results if we do not take this effect into account.
Synchronous Buck Converter
Figure 1 depicts a simplified synchronous buck converter. This topology is the workhorse of the PC power conversion industry, which offers an excellent combination of simplicity of operation, ease of control, high conversion efficiency and the allimportant low cost. We will concentrate on the conduction losses in both the M_{HS} and M_{LS} MOSFETs. The frequency effects of the dynamic losses will not be addressed in this paper. The switching current in both of these devices are a rectangular wave that that is represented in Figure 4.
Figure 1. Synchronous Buck Converter
Principles of operation
Assume the lower MOSFET, M_{LS}, is initially turned OFF and the top or control MOSFET, M_{HS}, is turned ON. This applies the input voltage to one end of the inductor, causing the inductor current to ramp up. When M_{HS} is turned OFF, the current will continue to flow through the inductor but now it flows through M_{LS }body diode. After a dead time on the order of a few tens of nanoseconds�dictated by the PWM controller�the MOSFET M_{LS} turns ON. This allows all the inductor current to flow through M_{LS} rather than its body diode since the voltage drop across its onresistance, is lower than the diode voltage drop.
Assuming that the current through the inductor does not reach zero (the Continuous Conduction Mode or CCM), the voltage across the lower MOSFET will simply be during the full OFF period of the top MOSFET where is the inductor current. At the end of the OFF period of the top MOSFET M_{HS}, the lower MOSFET, M_{LS}, will turn OFF, allowing the inductor current to flow in the body diode once more. After the dead time, the top MOSFET will turn ON and the cycle repeats. The average voltage at the output will depend on the average ON time of the top MOSFET if the inductor current is continuous. the output voltage V_{out} may be calculated from the equation where is the duty cycle and is equal to where is the on time of the control MOSFET and is the duration of one cycle where where is the converter switching frequency.
The conduction losses have traditionally been calculated from the equation where all parameters are self explanatory. We will demonstrate that this equation, though useful as a rough estimate, may not be accurate enough for accurate analysis.
The switching currents in M_{HS} and M_{LS} are approximately of a rectangular shape. Using Fourier analysis one may break it down to its constituent sinusoidal currents of frequencies where . Complete analysis is available later on in this worksheet.
Package Parasitic Resistance:
Due to the skin effect phenomenon, the bonding wires of the drain, gate and source leads exhibit different parasitic resistance at different frequencies.The package parasitic resistance is usually between for advanced packages to about 2.2 for the SO8 package and mainly depends on the bonding wires' diameter and length and their physical proximity to each other. This is a very small value that may be ignored in other small signal applications but in modern power circuits, we will show that it represents an appreciable part of the total onresistance of the switching device, which is the MOSFET for the purposes of this paper. To accurately determine the parasitic resistance it was important to isolate the package from the MOSFET silicon. To calculate the resistance as a function of frequency, we chose to employ finite element analysis (FEA) techniques.
This has the advantage of allowing us to determine very small resistance values without the need for special test equipment and fixtures. It also eliminated any error which will be introduced by the test environment. A harmonic analysis was used to model the magnetic field surrounding the package. Resistance is then determined by extracting the real part of the characteristic impedance ().Figure 2 shows both the SO8 and DPAK packages and all their constituents that affect the simulation. As can clearly be seen this is a fairly complex structure, which cannot readily yield a closed form function describing the parasitics. The approach we have taken was to fit a curve to the results of the finite element analysis performed at various frequencies. This curve then describes the parasitic resistance as a function of frequency. This is done so we can introduce this function in the loss equations which ultimately allows us to study the effect of this phenomenon on the predicted losses using DC onresistance as it is performed today.


Figure 2. Finite element Models for SO8 (left) and DPAK (right) power package

Figure 3 shows several curves for each package. The first in black is the calculated value of the parasitic resistance using finite element analysis and the red, blue and green curves are the plots of the fit function for 2nd, 3rd and 4th orders. The fit functions for several packages will be derived later in this paper. We have chosen to extend the simulation to 100 MHz to account for close examination of the loss equations up to a very high harmonic number.


Figure 3. Parasitic Resistance as a function of frequency for SO8 (left) and DPAK (right)

Figure 3 shows this effect clearly. The value of goes up by a full order of magnitude by changing the switching frequency from 30 KHz to a mere 10 MHz. This effect is very significant in switching MOSFETs since the device's onresistance is in the range of a few to start with.
Switching Drain Currents
Input Parameters
where = current rise time, = current fall time, =peak current, and = the inductor current at the start of M_{HS} on time.
The switching current is shown in Figure 4.
Figure 4. Switching Current Waveform
Each current cycle may be divided in four distinct regions as follows:
1. : the time for the MOSFET current to rise from to .
2. : the time duration of the M_{HS} switched fully on. During this time (the ontime) the inductor current ramps from to .
3. : when the M_{HS} is switched off, the MOSFET current starts falling from to .
4. : M_{HS} continues to be off while M_{LS} is turned on.
The first segment, , from may be expressed as .
The second segment, , is from may be expressed as .
The third segment from the drain current may be expressed as .
The last segment, , from and is .
The Fourier series of a periodic function with a period of 2l may be expressed in the form: where a0 is the averaged current.
Now we can calculate the average current a0 as well as an and bn:
By plotting both an and bn as a function of n, we can observe the envelope of the discrete values of both of them. The reason was chosen is that the highest frequency we deal with here is 2 MHz and the 50^{th} harmonic will be 100MHz which is the top value of frequency in our FEA.
In this paper we will only consider the top MOSFET M_{HS}. This is because in PC applications the duty cycle is relatively small ⩽ 12% resulting in a very rich harmonic content in the derived Fourier series for the switching current. The low side MOSFET M_{LS} has a duty cycle ⩾ 87% resulting in low harmonics and significantly less harmonics.
Now we can express the switching current in the Fourier series, , as:
Now let us verify the above results by plotting the Fourier series representation of the switching current:
As can be observed, it is the same as the waveform in Figure 4. One worthwhile observation is that the overshoot seen in the waveform is known as the Gibbs phenomenon, named after Josiah Willard Gibbs, the American mathematical physicist, as the phenomenon was noted by him in 1899. This overshoot appears in all Fourier series representation of any function with a jump similar to the above.
In order to calculate the losses, we must represent the term equivalently, in the form , where the peak amplitude An and the phase Φn are
and .
Since the phase value has no effect on power calculations, only is is needed for our calculation.
The root mean square (RMS) value of the amplitude is
Now the switching current , may be written as:
By plotting we can observe the envelope of the squared discrete current amplitudes.
The total MOSFET onresistance, , is made of two basic parameters:
1. The silicon onresistance, .
2. Package parasitic resistance, .
Thus,
The following are the Finite Element Analysis data for the SO8, DPAK and D2PAK packages:
where is the frequency in megahertz.
the raw parasitic resistance data for the SO8 package in mΩ.
the raw parasitic resistance data for the DPAK package in mΩ.
the raw parasitic resistance data for the D2PAK package in mΩ.
Using the Curve Fitting Assistant in Maple, we can fit curves for the parasitic resistance as a function of the frequency, , in megahertz, and the parasitic resistance in mΩ.
Each formula has a DC term and several frequency dependent terms. One further point: in this analysis, the minimum skin frequency is approximately 30 KHz for the packages used; below this frequency the skin effect may be considered zero. Therefore, these equations should be used to calculate the parasitic resistance for the frequency F, where . The DC value of the parasitic resistance is taken directly from the raw data. where n is the harmonic number and is the DCDC converter's switching frequency.
Now we can write the equation for the packaged MOSFET onresistance:
where is as before and is the silicon onresistance.
∴ The equations for for all the packages under consideration can be written as:
The above graph shows the parasitic resistance as a function of frequency for all three packages. Notice that the parasitic resistance can go as high as 500 at 100MHz for bonding wires of only when measured at DC.
∴ the total power dissipation may be written as:
We have replaced by 50 to facilitate graphing and calculations with reliable accuracy.
The traditional conduction loss calculations can be written as follows:
1. Calculate the RMS value of the current, , first:
2. Calculate the traditional conduction loss, :
Now we can derive a formula of the error using the traditional value vs. that using the frequency dependent parasitic resistance.
The percentage error (zaxes) as a function of the switching frequency
and the silicon onresistance for SO8, DPAK and D2PAK Package
The above graph depicts the percentage error between the calculation using the traditional formula vs. using the formulae derived above with skin effect taken into consideration.
Please notice that D2PAK will deliver 540% error when operating at 2 MHz and 2 mΩ onresistance. It is also worth noting that at a very low switching frequency, where fs ≤ 100 KHz, there is a negligible increase in parasitic resistance due to skin effect.
The ratio (z axis)
The above graph shows that in order to have efficient high frequency converters, designers must use advanced packages or they risk having inefficient power conversion leading to unacceptable power losses.
Conclusion
1. The package parasitic resistance represents an appreciable part of the MOSFET onresistance in power applications.2. The package parasitic resistance possesses a very strong frequency dependence due to the skin effect phenomenon.3. A higher fundamental switching frequency will result in higher parasitic resistance and hence higher conduction losses.4. The DC conduction losses calculated above produce an error that can be as large as 500% depending on the package and the fundamental switching frequency.
5. When choosing the switching frequency for a given application, it is mandatory to examine this above mentioned effect to weigh the pros and cons of such a selection.6. New packages have been developed by several manufacturers that address this problem with varying degrees of success. Some are very successful like DirectFet BGA. 7. As the DCDC converters are expected to perform at higher efficiencies, particularly in the notebook field, all loss mechanisms must be placed under the microscope in an attempt to minimize their effect and provide the overall solution that fully utilizes all the advantages made so far in MOSFET design.8. Both with breakthroughs in silicon and in innovative packaging, these new switching devices continue to deliver improvement in performance at very reasonable prices .
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